Peripheral systems attachable to host central processing units (CPUs) have become an increasing portion of the total cost of a data processing facility. These increased costs had been particularly true in plural CPU systems employing data storage devices. A reason for the increased costs is the increasing demand for higher and higher performance of a data processing facility. Diverse peripheral system control techniques have been used to enhance performance of peripheral systems, while still trying to control increasing costs.
An approach to provide higher performance is to design the peripheral devices with higher performance. This, of course, adds to the cost of such peripheral devices. As an example, magnetic tape recording devices have employed vacuum columns as a mechanical buffer between a large reel of tape and a transducing station. Such vacuum columns, particularly in an extremely high-performance unit require complex controls, as well as expensive mechanical portions. Accordingly, it is desired to reduce the cost of peripheral systems by utilizing lower performance peripheral devices, yet maintain the overall high performance expected from a peripheral system. The present invention achieves this goal by providing a unique arrangement in a peripheral system that is a substantial change from prior art systems.
Most connections and control systems interposed between a peripheral device and a host CPU attempt to maximize data transfer performance. Of course, performance can be enhanced by maximizing the socalled burst rate, that is, how fast digital signals can be transferred through an electrical interface. Other control features, such as selection of a device for a particular computer program being executed within a host CPU error recovery and the like also impact performance. To this end, the system shown in E. R. Marsh, U.S. Pat. No. 3,377,609, and the interface shown in publication A22-6974-X, file No. S/360-S370-XX and entitled, "IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturers Information" (OEMI) available from International Business Machines Corporation, Data Processing Division, 1133 West Avenue, White Plains, N.Y., 01604, show such an interface system. An important aspect of a peripheral storage system is integrity of the data being transferred and stored in the peripheral system. This interface arrangement, which is well known and widely used in a data processing art, can be applied to a control unit to device connection. In fact, several connections between control units and peripheral devices employ the principles of this host CPU to control unit connection. That is, a typical peripheral system attached to a channel of a host CPU includes a so-called control unit which in turn is connected to a plurality of peripheral devices. In some peripheral systems, a plurality of control units can be interconnected to an array of devices for multiplexing and multipathing purposes. These connections usually involve status signal data lines, commonly referred to as bus-out and bus-in for synchronously transferring data signals. The bus-out term applies to signals transferred from the host CPU to the control unit or from the control unit to the peripheral device. Bus-in lines are those lines that transfer signals from the peripheral device to the control unit or from control unit to the host CPU. Additionally, a set of tag or control lines for selecting, controlling and deselecting a control unit by a host CPU accompany the bus-in and bus-out lines. Such lines perform similar functions between a control unit and its peripheral devices. Generally, the connection between a control unit and peripheral device is somewhat simpler than that used in connecting a control unit to a host CPU. Two or more of the tag lines can be used to synchronize the operation of the data lines. Many connections are in a so-called "daisy-chain" arrangement, wherein a plurality of connections are made in a single circuit, such that one device or one control unit can operate with only one device at a time.
The tag lines operate in a somewhat asynchronous manner. That is, they are not data-synchronous. The tag lines are interlocked, such that one tag signal will not be removed until a responding tag signal has been sent. Such interlocking provides for the asynchronous operation while maintaining high integrity in the connection. Operation of the tag lines or the asynchronous path of control always precedes the actual data transfer. In other words, immediate device or control unit preparation and data transfer occur in one selection process. Of course, so-called "free-standing" operations can occur where the device or control unit disconnects from the controlling unit, respectively, the control unit or host CPU. Such free-standing operations for a device include rewinding of tape to beginning of tape (BOT), erasing to the end of the tape, and the like. Such free-standing operations permit limited overlap of device operation for improving peripheral system efficiency and performance. A modification of the above-described connection is shown in Levy et al., U.S. Pat. No. 3,999,163, which describes a secondary or peripheral storage facility. This patent shows synchronous and asynchronous paths wherein the asynchronous path is expanded over the asynchronous tag lines shown in the first-described connection. In Levy et al., status and controller information is coupled between the controller and a selected drive unit asynchronously over an asynchronous bus. Actual data transfers (user data transfers) occur between the controller and the drive (herein referred to as device) over a synchronous bus and between other units in the system and the controller using a direct memory access or equivalent data transfer technique.
The asynchronous drive control path includes data, address and control lines. The signals over the asynchronous path perform control functions and include control signals for effecting information transfers to or from addressed storage locations in the drive. The starting address in the drive and the sizes of the immediately ensuing data transfer over the synchronous bus are typical items of information which are sent to the drive over the asynchronous path. The synchronous data path which transfers the data itself, also contains data and some control lines. Control lines carry signals used for synchronizing the controller and drive, starting a data transfer and signaling any malfunctions which might occur during a data transfer.
The signals on the asynchronous and synchronous data paths constitute a standard set of signals which control diverse units, such as disk drives, magnetic tape drives, and so forth. Therefore, Levy et al. teach that a controller can be made independent of the drive it controls so that diverse units can be connected to one controller. This type of connection still may not provide for maximizing overlap of device operations nor for maximizing efficiency of a peripheral system such that higher and higher performance can be achieved at lower and lower costs. Costs may be reduced by sharing the controller to diverse types; however, it does not follow that a maximal performance can be achieved from the connected devices. Therefore, higher performance devices appear to still be required with the Levy et al. system for achieving high peripheral system performance.
Accordingly, it is desired to find an arrangement for a peripheral system which provides high performance with relatively low performance devices and at a reasonable cost.